Decoupling Capacitor Optimization for Nanotechnology Designs

被引:1
作者
Bozorgzadeh, Bardia [1 ]
Afzali-Kusha, Ali [1 ]
机构
[1] Univ Tehran, Nanoelect Ctr Excellence, Sch Elect & Comp Engn, Tehran, Iran
来源
2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2008年
关键词
Decoupling Capacitor; Nanotechnology; Optimization; Power Supply Noise;
D O I
10.1109/ICM.2008.5393765
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
On-chip MOS decoupling capacitors (DECAPs) are widely used to reduce power supply noise. Designing DECAP in nanotechnology designs provides many challenges. In this paper first it is shown that all of these challenges are functions of the DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied to 45nm and 32nm technology nodes and the results are extracted using HSPICE simulations. The results show that the optimum channel length of MOS DECAPs depends on the technology node and operating frequency. Finally, based on the results, two optimum DECAP configurations which provide trades off among area and gate leakage for different applications in nanotechnologies are proposed.
引用
收藏
页码:19 / 22
页数:4
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