A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS

This paper presents a successive approximation register (SAR) assisted hybrid analog to digital converter (ADC) that uses a time domain quantizer for sub-range quantization. The proposed hybrid ADC utilizes an 8b 2bit-per-cycle SAR coarse ADC pipelined with a 6b 2-dimensional Vernier time-to-digital converter (TDC) as the fine quantizer for high-resolution and high conversion rate. Different from the conventional approach, the voltage residue is converted into time domain for fine quantization which greatly relaxes the power-to-noise requirement of the comparator for high-resolution. Moreover, the 8b coarse quantization stage greatly reduces the range of the residue signal and thus dramatically relieves the linearity requirement of the voltage-to-time (V-T) conversion. The LSB of the TDC is digitally calibrated thus the gain accuracy of the pipeline stage is relaxed. The prototype was fabricated in a 45nm CMOS process, and the ADC core dissipates 3.66 mA from a 1-V supply with an active area of 0.08mm(2). The prototype chip achieves a measured peak SNDR of 65.7dB and SFDR of 80.7dB at conversion rate up to 280MS/s. The calculated Walden and Schreier figures-of-merit (FoM) are 8.4fJ/conv.-step and 171.5dB, respectively.