Design of high-speed CMOS frequency dividers for RF receiver

被引：0

作者：

Tang, Lu ^{[1
]}

Wang, Zhi-Gong ^{[1
]}

He, Xiao-Hu ^{[1
]}

Li, Zhi-Qun ^{[1
]}

Xu, Yong ^{[1
,2
]}

机构：

[1] Southeast Univ, Inst RF & OE ICs, Nanjing 120096, Peoples R China

[2] PLA Univ Sci Technol, Inst Sci, Nanjing PT-211101, Peoples R China

来源：

2007 5TH INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A divide-by-16/17 dual-modulus prescaler (DMP) and two programmable & plus swallow dividers for application in a Digital Video Broadcasting-Terrestrial (DVB-T) receiver are designed in a 0.18 mu m 3.3V mixed-signal CMOS process. The master/slave D-Flip-Flop (DFF) in the DMP is made up of an improved D-latch to increase the speed and the driving capability; A novel D-latch architecture integrated with 'OR' logic is proposed to decrease the complexity of the circuit. Post simulation results of the chip layout indicate that the proposed DMP works well at the frequency band of 1 similar to 2 GHz. The maximum operating speed is 2.4 GHz. The programmable & plus swallow dividers are directly synthesized by EDA tools and finally fabricated with 0.18 mu m standard library.

引用

页码：552 / +

页数：2

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