Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications

In this paper, nonlinear and low-power resistive switching characteristics of Si3N4-based RRAM embedding SiO2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO2 layer. Furthermore, we offer an optimized solution by modulating compliance current (I-CC), read voltage (V-READ), and TB thickness for higher selectivity. Low current operation tuned by I-CC, V-READ, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications. (C) 2015 Elsevier B.V. All rights reserved.