VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

被引：66

作者：

Choi, Hyojin ^{[1
]}

Liu, Wei

Sung, Wonyong ^{[1
]}

机构：

[1] Seoul Natl Univ, Sch Elect Engn, Seoul 151744, South Korea

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2010年 / 18卷 / 05期

关键词：

Bose-Chaudhuri-Hocquenghem (BCH) code; memory error correction; NAND Flash memory; solid-state drive (SSD); HIGH-SPEED ARCHITECTURES; ENCODERS;

D O I：

10.1109/TVLSI.2009.2015666

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) NAND Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.

引用

页码：843 / 847

页数：5

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