Tree-Permutation-Matrix Based LDPC Codes

被引:3
作者
Jiang, Sheng [1 ]
Mo, Fanlu [1 ]
Lau, Francis C. M. [1 ]
Sham, Chiu-W [2 ]
机构
[1] Hong Kong Polytech Univ, Dept Elect & Informat Engn, Hong Kong, Hong Kong, Peoples R China
[2] Univ Auckland, Dept Comp Sci, Auckland 1142, New Zealand
关键词
FPGA implementation; low-density parity-check code; tree-permutation matrix; PARITY-CHECK CODES; DECODER;
D O I
10.1109/TCSII.2017.2785779
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-density parity-check (LDPC) codes are normally categorized into random structure or regular structure. In this brief, we introduce a new type of LDPC codes which is of semi-regular style. The parity-check matrices of the new LDPC code type are composed of sub-matrices termed tree-permutation matrices (TPMs). These TPMs are "semi-regular" and are constructed in a systematic way. Using the 2 x 2 identity matrix and anti-diagonal matrix as an example, we illustrate how 2(M) x 2(M ) TPMs are formed. During the formation of the 2(M) x 2(M) TPMs, we further apply the hill-climbing algorithm to avoid short cycles. Finally, we construct a girth-8 TPM-LDPC code with a base matrix of size 4 x 24 and a girth-10 TPM-LDPC code with a base matrix of size 3 x 10. We implement the TPM-LDPC decoders on an FPGA and compare the simulation results and decoder complexity with other LDPC codes.
引用
收藏
页码:1019 / 1023
页数:5
相关论文
共 13 条
[1]   A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications [J].
Cheng, Chung-Chao ;
Yang, Jeng-Da ;
Lee, Huang-Chang ;
Yang, Chia-Hsiang ;
Ueng, Yeong-Luh .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (09) :2738-2746
[2]   On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit [J].
Chung, SY ;
Forney, GD ;
Richardson, TJ ;
Urbanke, R .
IEEE COMMUNICATIONS LETTERS, 2001, 5 (02) :58-60
[3]   Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes [J].
Dai, Yongmei ;
Chen, Ning ;
Yan, Zhiyuan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (09) :2898-2911
[4]   Quasi-cyclic low-density parity-check codes from circulant permutation matrices [J].
Fossorier, MPC .
IEEE TRANSACTIONS ON INFORMATION THEORY, 2004, 50 (08) :1788-1793
[5]   LOW-DENSITY PARITY-CHECK CODES [J].
GALLAGER, RG .
IRE TRANSACTIONS ON INFORMATION THEORY, 1962, 8 (01) :21-&
[6]  
Lau FCM, 2017, INT CONF ADV COMMUN, P497, DOI 10.23919/ICACT.2017.7890139
[7]  
Lau FCM, 2012, 2012 IEEE SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS (ISCC), P125, DOI 10.1109/ISCC.2012.6249279
[8]   A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes [J].
Lu, Qing ;
Fan, Jianfeng ;
Sham, Chiu-Wing ;
Tam, Wai M. ;
Lau, Francis C. M. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (01) :134-145
[9]   A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes [J].
Sham, Chiu-Wing ;
Chen, Xu ;
Lau, Francis C. M. ;
Zhao, Yue ;
Tam, Wai M. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2013, 60 (07) :1857-1869
[10]  
Smarandache R., 2011, P IEEE INT C COMM KY, P1