A 13-ENOB, 5 MHz BW, 3.16 mW Multi-Bit Continuous-Time ΔΣ ADC in 28 nm CMOS with Excess-Loop-Delay Compensation Embedded in SAR Quantizer

被引：0

作者：

Wei, Guowen ^{[1
]}

Shettigar, Pradeep ^{[1
]}

Su, Feng ^{[1
]}

Yu, Xinyu ^{[1
]}

Kwan, Tom ^{[1
]}

机构：

[1] Broadcom Corp, 3151 Zanker Rd, San Jose, CA USA

来源：

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 13-ENOB, 5 MHz BW, 3.16 mW 3-bit continuous-time Delta Sigma ADC sampling at 432 MHz is presented. For power efficiency, this design utilizes a hybrid feedback feed-forward loop topology with SAR quantizer, feed-forward compensated amplifiers, and push-pull DACs. Further power efficiency is gained by performing excess-loop-delay compensation (ELDC) using the SAR quantizer SC-DAC, which reduces power overhead from ELDC to a negligible level. A 94 dB SFDR is achieved through feedback-DAC calibration. The 0.066 mm(2) design is fabricated in 28 nm CMOS and achieves FoMs of 36.4 fJ/step and 175.9 dB.

引用

页数：2

共 2 条

[1] A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time DeltaSigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation
Weng, Chan-Hsiang
Lin, Chen-Chien
Chang, Yu-Cheng
Lin, Tsung-Hsien
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (12) : 867 - 871
[2] A 24 mW, 80 dB SNR, 50 MHz multi-bit continuous time ΣΔ ADC in 28 nm FD-SOI
Chopra, Anubhuti
Chatterjee, Shouri
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 65 - 68

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