How to use high speed reconfigurable FPGA for real time image processing?

被引：12

作者：

Demigny, D ^{[1
]}

Kessal, L ^{[1
]}

Bourguiba, R ^{[1
]}

Boudouani, N ^{[1
]}

机构：

[1] ENSEA, F-95014 Cergy Pontoise, France

来源：

5TH INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURES FOR MACHINE PERCEPTION, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/CAMP.2000.875983

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In France, ten research teams study and build an hardware architecture (ARDOISE) which is dedicated to real time image processing. This architecture uses fast or dynamic reconfiguration allowed by new FPGA circuits. During a video frame duration, several algorithms are computed sequentially on the same hardware. This paper highlights the architectural concepts used to build ARDOISE. Then an analytical model is defined ill order to compute the limits and the performances expected in the use of the dynamic reconfiguration scheme. An example in image segmentation is developed to show a possible partitioning methodology.

引用

页码：240 / 246

页数：7

共 6 条

[1]

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[2]

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[3]

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[4]

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[6]

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