Systolic array implementation of block LMS algorithm

被引：1

作者：

Yoshida, T ^{[1
]}

Iiguni, Y ^{[1
]}

Maeda, H ^{[1
]}

机构：

[1] Osaka Univ, Grad Sch Engn, Dept Commun Engn, Suita, Osaka 565, Japan

来源：

ELECTRONICS LETTERS | 1998年 / 34卷 / 07期

关键词：

D O I：

10.1049/el:19980493

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The authors derive the systolic array implementation of the block LMS algorithm, consisting of N processing elements, where N is the filter order. The resulting array attains an order-independent sampling rate. Computer simulation results show that the block LMS algorithm is faster than the delayed LMS algorithm. which has previously been implemented on systolic arrays.

引用

页码：637 / 638

页数：2

共 3 条

[1]

CHESTER DB, 1991, INT CONF ACOUST SPEE, P2109, DOI 10.1109/ICASSP.1991.150822

[2] A SYSTOLIC ARRAY REALIZATION OF AN LMS ADAPTIVE FILTER AND THE EFFECTS OF DELAYED ADAPTATION [J].

HERZBERG, H ;

HAIMICOHEN, R ;

BEERY, Y .

IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1992, 40 (11) :2799-2803

[3] A HIGH SAMPLING RATE DELAYED LMS FILTER ARCHITECTURE [J].

MEYER, MD ;

AGRAWAL, DP .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1993, 40 (11) :727-729

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