Etch and strip induced material modification of porous low-k (k=2.2) dielectric

被引：27

作者：

Furukawa, Y

Wolters, R

Roosen, H

Snijders, JHM

Hoofman, R

机构：

[1] Philips Res Leuven, B-3001 Heverlee, Belgium

[2] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

[3] Philips Ctr Ind Technol, NL-5656 AA Eindhoven, Netherlands

来源：

MICROELECTRONIC ENGINEERING | 2004年 / 76卷 / 1-4期

关键词：

low-k dielectrics; plasma; modification; sidewall; XPS; CVD;

D O I：

10.1016/j.mee.2004.07.017

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

XPS analysis on the sidewall surface of Orion2.2, a CVD SiOC type low-k dielectric (k approximate to 2.2), has been performed to study the modification of low-k material during etching and strip. The sidewall surface etched in Ar/CF4/CH2F2/O-2 consists of two layers, a CFx polymer and behind that a SiOC(F) layer. No carbon depletion was observed on the sidewall surface due to protection by the CFx polymer layer against plasma damage. All plasma strip using CF4/O-2, N-2/O-2, N-2/H-2 or H-2/He chemistry remove CFx polymer layer and PR efficiently, however it gives C-depletion of low-k material. The strip using H-2/He has minimum damage of low-k material and no N contamination although it cannot eliminate fluorine contamination, which may cause voids in low-k material. (C) 2004 Elsevier B.V. All rights reserved.

引用

页码：25 / 31

页数：7

共 17 条

[1]

ABELL T, 2003, P ADV MET C 2002 MAT, P919

[2] Porous dielectric Dual Damascene Patterning issues for 65nm node : Can architecture bring a solution? [J].

Assous, M ;

Simon, J ;

Broussous, L ;

Bourlot, C ;

Fayolle, M ;

Louveau, O ;

Roman, A ;

Tabouret, E ;

Feldis, H ;

Louis, D ;

Torres, J .

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, :97-99

[3]

Bohr MT, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P241, DOI 10.1109/IEDM.1995.499187

[4] The novel improvement of low dielectric constant methylsilsesquioxane by N2O plasma treatment [J].

Chang, TC ;

Liu, PT ;

Mor, YS ;

Sze, SM ;

Yang, YL ;

Feng, MS ;

Pan, FM ;

Dai, BT ;

Chang, CY .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1999, 146 (10) :3802-3806

[5] Process integration of Cu metallization and ultra low k (k=2.2) [J].

Cheng, C ;

Hsia, W ;

Pallinti, J ;

Neumann, S ;

Koh, J ;

Li, P ;

Zhu, M ;

Lu, M ;

Cui, H ;

Fujimoto, T ;

Catabay, B ;

Wright, P .

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, :256-258

[6]

DONOHUE H, 2002, ADV MET C AMC, P575

[7] Integration of Cu/SiOC in Cu dual damascene interconnect for 0.1-μm technology [J].

Fayolle, M ;

Torres, J ;

Passemard, G ;

Fusalba, F ;

Fanget, G ;

Louis, D ;

Assous, M ;

Louveau, O ;

Rivoire, M ;

Haxaire, K ;

Mourier, M ;

Maitrejean, S ;

Besson, P ;

Broussous, L ;

Arnaud, L ;

Feldis, H .

MICROELECTRONIC ENGINEERING, 2002, 64 (1-4) :35-42

[8] Material modification of the patterned wafer during dry etching and strip determined by XPS [J].

Furukawa, Y ;

Patz, M ;

Kokubo, T ;

Snijders, JHM .

MICROELECTRONIC ENGINEERING, 2003, 70 (2-4) :267-273

[9]

Hens S, 2001, INST PHYS CONF SER, P415

[10] A manufacturable Copper/low-k SiOC/SiCN process technology for 90nm-node high performance eDRAM [J].

Higashi, K ;

Nakamura, N ;

Miyajima, H ;

Satoh, S ;

Kojima, A ;

Abe, J ;

Nagahata, K ;

Tatsumi, T ;

Tabuchi, K ;

Hasegawa, T ;

Kawashima, H ;

Arakawa, S ;

Matsunaga, N ;

Shibata, H .

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, :15-17

← 1 2 →