A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications The different clock frequencies can be generated with the particular phase combinations of a blur-stage voltage-controlled oscillator (VCO) It has been fabricated in a 0 13 mu m CMOS technology, and work with a supply voltage of 1 2 V According to measured results the frequency ranee of the proposed pseudo fractional-N clock generator is from 71 4 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period Duty cycle error rates of the output clock frequencies are from 0 8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 mu W at 304 MHz