Further Study of the U-Shaped Channel SOI-LIGBT With Enhanced Current Density for High-Voltage Monolithic ICs

被引:38
作者
Zhu, Jing [1 ]
Zhang, Long [1 ]
Sun, Weifeng [1 ,2 ]
Du, Yicheng [1 ]
Huang, Keqin [1 ]
Chen, Meng [1 ]
Shi, Longxing [1 ]
Gu, Yan [3 ]
Zhang, Sen [3 ]
机构
[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Jiangsu, Peoples R China
[2] Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, Shanghai 200433, Peoples R China
[3] CSMC Technol Corp, Wuxi 214028, Peoples R China
基金
中国国家自然科学基金;
关键词
Current density; latch-up voltage; short-circuit withstand time; silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT); U-shaped channel; TRENCHES;
D O I
10.1109/TED.2016.2520466
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A high-voltage silicon-on-insulator lateral insulatedgate bipolar transistor (SOI-LIGBT) with U-shaped channels, which are composed of parallel channels and orthogonal channels for improving the current density (J(C)) and latch-up immunity, is proposed and studied intensively in this paper. By using the U-shaped channels, the electron injection from the emitter into the n-drift region is significantly enhanced, and the current density is improved. In addition, an analytical model is proposed, and it is indicated that J(C) can be improved as a (the angle between the parallel channel and the orthogonal channel) increases in a certain range. The hole current density distribution in the ON-state and the lattice temperature distribution in the short-circuit state of the proposed structure are also investigated. Increasing a is beneficial to alleviate the holes crowding beneath the n(+) emitter and suppress the temperature rise in the JFET region, which is favorable for increasing the latch-up voltage (VLP) and short-circuit withstand time (t(SC)). The experiments demonstrate that the U-shaped channel SOI-LIGBT fabricated with 0.5-mu m SOI technology exhibits a high current density (J(C)) of 305 A/cm(2) at V-CE = 3 V and V-GE = 5 V, and a low specific ON-resistance (R-ON.sp) of 0.984 Omega . mm(2) with breakdown voltage of 590 V. The improved latch-up voltage (V-LP) of 560 V and the short-circuit withstand time (t(SC)) of 5.1 mu s are obtained.
引用
收藏
页码:1161 / 1167
页数:7
相关论文
共 16 条
[1]  
CHOO SC, 1970, IEEE T ELECTRON DEV, VED17, P647, DOI 10.1109/T-ED.1970.17051
[2]  
Funaki H, 1997, ISPSD '97: 1997 IEEE INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, P33, DOI 10.1109/ISPSD.1997.601424
[3]  
Hara K, 2014, PROC INT SYMP POWER, P418, DOI 10.1109/ISPSD.2014.6856065
[4]  
Liu SY, 2013, PROC INT SYMP POWER, P115, DOI 10.1109/ISPSD.2013.6694442
[5]  
Lu DH, 2008, INT SYM POW SEMICOND, P32
[6]  
Lu DH, 2005, INT EL DEVICES MEET, P393
[7]  
Nakagawa A., 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312), P321, DOI 10.1109/ISPSD.1999.764125
[8]  
Sakano J, 2010, PROC INT SYMP POWER, P83
[9]   A Novel Silicon-on-Insulator Lateral Insulated-Gate Bipolar Transistor With Dual Trenches for Three-Phase Single Chip Inverter ICs [J].
Sun, Weifeng ;
Zhu, Jing ;
Zhang, Long ;
Yu, Hui ;
Du, Yicheng ;
Huang, Keqin ;
Lu, Shengli ;
Shi, Longxing ;
Yi, Yangbo .
IEEE ELECTRON DEVICE LETTERS, 2015, 36 (07) :693-695
[10]  
Takahashi S, 2012, PROC INT SYMP POWER, P393, DOI 10.1109/ISPSD.2012.6229104