Low-Noise Fractional-N PLL With a High-Precision Phase Control in the Phase Synchronization of Multichips

被引：7

作者：

Huang, Sheng ^{[1
]}

Liu, Shubin ^{[1
]}

Liu, Maliang ^{[1
]}

Hu, Jin ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Shaanxi Key Lab Integrated Circuits & Syst, Xian 710071, Shaanxi, Peoples R China

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2018年 / 28卷 / 08期

基金：

中国国家自然科学基金;

关键词：

Phase-locked loop (PLL); phase synchronization; sigma-delta modulator (SDM); voltage-controlled oscillator (VCO);

D O I：

10.1109/LMWC.2018.2842680

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents a low noise fractional-N phase-locked loop (PLL) with a high-precision phase control. The resistors in loop filter and the current in the charge pump can be adjusted to achieve a reconfigurable loop bandwidth. A method to adjust the phase of the fractional-N PLL with high precision is proposed, which can be applied in the phase synchronization of multichips. The function of a high-accuracy phase control is added to the proposed sigma-delta modulator without adjusting the frequency division ratio. The prototype chip was fabricated using a 0.18-mu m CMOS process with an active area of 1.8 mm(2). With a 1.8-V power supply, a reference frequency of 19.2 MHz, and a 2-GHz output radio frequency clock, this prototype achieves phase noise -122 dBc/Hz at 1 MHz while drawing 11.3 mW.

引用

页码：702 / 704

页数：3

共 7 条

[1] A 0.5 V 5.96-GHz PLL With Amplitude-Regulated Current-Reuse VCO [J].