Design of All-Directional ESD Protection circuit with SCR-based I/O and LIGBT-based Power clamp

被引:8
作者
Do, Kyoung-Il [1 ]
Jin, Seung-Hoo [1 ]
Lee, Byung-Seok [1 ]
Woo, Je-Wook [1 ]
Koo, Yong-Seo [1 ]
机构
[1] Dankook Univ, Dept Engn Elect & Elect, Yongin, South Korea
来源
2021 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2021年
基金
新加坡国家研究基金会;
关键词
ESD; SCR; GGNMOS; LIGBT; Holding Voltage; Trigger Voltage; Reliability;
D O I
10.1109/ICEIC51217.2021.9369761
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposed whole-chip all-directional ESD protection circuit design with RC LIGBT-based 12 V Power clamp and SCR-based 12 V I/O Clamp. The proposed ESD protection circuit is fabricated using a 0.18 mu m Bipolar-CMOS-DMOS (BCD) process. To analysis electrical properties and robustness was analyzed by TLP (Transmission Line Pulse) system, and with an ESD pulse generator. The results of the measurement indicate that in the case of the RC LIGBT power clamp for HBM 8 kV and MM 800V in stress mode DS (VDD to VSS). Additionally, SCR-based ESD protection circuit for I/O can discharge ESD current in four stress mode (PD: positive VDD, ND: negative -VDD, PS: positive -VSS, NS: negative -VSS) with superior characteristics for HBM 8kV, MM 800V.
引用
收藏
页数:3
相关论文
共 4 条
[1]  
Ground E., 2007, EOSESD S
[2]   Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits [J].
Ker, MD ;
Hsu, KC .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (02) :235-249
[3]   Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test [J].
Ker, Ming-Dou ;
Yen, Cheng-Cheng .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (11) :2533-2545
[4]   High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps [J].
Vashchenko, VA ;
Concannon, A ;
ter Beek, M ;
Hopper, P .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (02) :273-280