Thermosonic wire bonding process simulation and bond pad over active stress analysis

被引：19

作者：

Liu, Y ^{[1
]}

Irving, S ^{[1
]}

Luk, T ^{[1
]}

机构：

[1] Fairchild Semicond Corp, Portland, ME 04106 USA

来源：

54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/ECTC.2004.1319369

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a transient non-linear dynamic finite element framework is developed, which integrates the wire bonding process and the silicon devices under bond pad. Two major areas are addressed: one is the impact of assembly Is' wire bonding process and another one is the impact of device layout below the bond pad. Simulation includes the ultrasonic transient dynamic bonding process and the stress wave transferred to bond pad device and silicon in the 1(st) bond. The Pierce strain rate dependent model is introduced to model the impact stain hardening effect. Ultrasonic amplitude and frequency are studied and discussed for the bonding process. In addition, different layouts of device metallization under bond pad are analyzed and discussed for the efforts to reduce the dynamic impact response of the bond pad over active (BPOA) design. Modeling discloses the stress and deformation impacts to both wire bonding and pad below device with strain rate, different ultrasonic amplitudes and frequencies, different friction coefficients, as well as different bond pad thickness and device layout under pad. The residual stress, after cooling down to a lower temperature, is discussed for the impact of substrate temperature.

引用

页码：383 / 391

页数：9

共 10 条

[1]

Gillotti G., 2002, SEMICON W 2002 SEMI

[2]

HARMAN GG, 1997, WIRE BONDING MICROEL

[3]

Hess K.J., 2003, P 53 EL COMP TECHN C

[4] Failure estimation of semiconductor chip during wire bonding process [J].