Design and testing of an integrated circuit for multi-electrode neural recording

被引:4
作者
Harrison, Reid R. [1 ,1 ]
Watkins, Paul T.
Kier, Ryan J.
Black, Daniel J. [1 ]
Lovejoy, Robert O. [1 ]
机构
[1] Univ Utah, Dept Bio Engn, Salt Lake City, UT 84112 USA
来源
20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA | 2007年
关键词
D O I
10.1109/VLSID.2007.63
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We have developed a single-chip neural recording system with wireless power delivery and telemetry. The 0.5-mu m CMOS IC is designed to be bonded to the back of a 100-channel Utah Electrode Array. A pad near each amplifier allows connection of the chip to the MEMS electrode array. The complete Integrated Neural Interface will receive power wirelessly through a 2.64-MHz inductive link. A clock, regulated supply, and commands are derived from the power signal. The neural amplifiers each have a gain of 60 dB. A 10-bit charge-redistribution ADC is used to digitize the signal from one amplifier selected with an analog MUX Digitizing all channels simultaneously would generate prohibitively high data rates; therefore, we perform data reduction by incorporating one-bit "spike detectors" into each amplifier. Neural data is transmitted off chip using an -integrated 433-MHz FSK transmitter. The chip measures 4.7x5.9 mm(2) and consumes 13.5 mW of power.
引用
收藏
页码:907 / +
页数:2
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