A Fault-Tolerant and Congestion-Aware Routing Algorithm for Networks-on-Chip

被引：0

作者：

Valinataj, Mojtaba ^{[1
,2
]}

Mohammadi, Siamak ^{[1
]}

Plosila, Juha ^{[2
]}

Liljeberg, Pasi ^{[2
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran, Iran

[2] Univ Turku, Dept Informat Technol, Turku, Finland

来源：

PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2010年

关键词：

Network-on-Chip; fault-tolerance; routing algorithm; traffic; reconfiguration;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a fault-tolerant routing algorithm for mesh-based Networks-on-Chip (NoC) with faulty links. It is a distributed, adaptive and congestion-aware routing algorithm where only two virtual channels are used for both adaptiveness and fault-tolerance. The proposed routing method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty links in more complicated faulty situations with additional hardware costs. The network performance, fault-tolerance capability and hardware overhead are evaluated through appropriate simulations. The experimental results show that the overall reliability of a Network-on-Chip is significantly enhanced against multiple link failures or partially faulty routers with only a small hardware overhead.

引用

页码：139 / 144

页数：6

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