Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

被引：0
|
作者：
Pant, P [1 ]
Roy, RK [1 ]
Chatterjee, A [1 ]
机构：
[1] Georgia Inst Technol, Atlanta, GA 30332 USA
来源：
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic CMOS circuit for a dual-threshold voltage process. The tradeoff between static and dynamic poser consumption has been explored. When Used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of the circuits by as much as 50%.
引用
收藏
页码：26 / 29
页数：4
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