High-Speed FPGA Implementation for DWT of Lifting Scheme

被引：0
|
作者：
Wang, Wei [1 ]
Du, Zhiyun [1 ]
Zeng, Yong [1 ]
机构：
[1] Chongqing Univ Posts & Telecommun, Coll Elect Engn, Chongqing 400065, Peoples R China
来源：
2009 5TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-8 | 2009年
关键词：
Discrete wavelet transform (DWT); lifting scheme; multi-stage pipelining; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new approach for Discrete Wavelet Transform (DWT) has been proposed recently under the name of lifting scheme. This scheme presents many advantages over the convolution-based approach. In this paper, a high speed 9/7 lifting DWT algorithm which is implementation on FPGA with multi-stage pipelining structure and rational 9/7 coefficients is presented. Compared with the architecture without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 3 times more fast, at the expense of about 40% more hardware area. The hardware architecture is suitable for high speed implementation.
引用
收藏
页码：2096 / 2099
页数：4
相关论文
共 50 条
  • [1] Implementation of Lifting Scheme Based DWT Architecture on FPGA
    Bhat, Naagesh S.
    PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, 2013, 174 : 361 - 369
  • [2] High Speed VLSI implementation of Lifting Based DWT
    Nageswaran, Usha Bhanu
    Chilambuchelvan, A.
    PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI'12), 2012, : 1104 - 1110
  • [3] VLSI architecture for high-speed/low-power implementation of multilevel lifting DWT
    Mohanty, Basant K.
    Meher, Pramod K.
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 458 - +
  • [4] High performance hardware implementation architecture for DWT of lifting scheme
    Hao, Yanling
    Liu, Ying
    Wang, Renlong
    2008 FOURTH INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING, PROCEEDINGS, 2008, : 1255 - 1258
  • [5] High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme
    Ferozpuri, Ahmed
    Gaj, Kris
    2018 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2018,
  • [6] Modified Lifting Scheme Algorithm for DWT with Optimized Latency & Throughput and FPGA Implementation for Low Power & Area
    Mohan, Murali S.
    Sathyanarayana, P.
    2016 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER APPLICATIONS (ICACA), 2016, : 351 - 356
  • [7] Pipelined architecture for high-speed implementation of multilevel lifting 2-D DWT using 9/7 filters
    Mohanty, Basant K.
    Meher, Promod K.
    ISSCS 2007: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2007, : 137 - +
  • [8] High-speed FPGA Implementation of an Improved LMS Algorithm
    Dong, Xianglei
    Li, Huiyong
    Wang, Yu
    2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PROBLEM-SOLVING (ICCP), 2013, : 342 - 345
  • [9] The Design and Implementation of High-Speed Codec Based on FPGA
    Ren, Weiji
    Liu, Hao
    2018 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION SOFTWARE AND NETWORKS (ICCSN), 2018, : 427 - 432
  • [10] Lifting Scheme DWT Implementation in a Wireless Vision Sensor Network
    Ong, Jia Jan
    Ang, L. -M.
    Seng, K. P.
    VISUAL INFORMATICS: BRIDGING RESEARCH AND PRACTICE, 2009, 5857 : 627 - 635
12345