A novel technique integrating buffer insertion into timing driven placement*

被引:0
作者
Luo, Lijuan [1 ]
Zhou, Qiang [1 ]
Cai, Yici [1 ]
Hong, Xianlong [1 ]
Wang, Yibo [1 ]
机构
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
来源
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
基金
美国国家科学基金会;
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Increasing buffer number for future technology makes traditional one-pass-flow (timing driven placement is followed by buffer insertion and legalization) failed, since accommodation for buffers significantly disturbs original design, This paper exploits the delicate relationship between buffer insertion and timing driven placement, and proposes a novel method to incorporate buffer insertion during timing driven placement. Experimental results show that this incorporation not only ensures design convergence, but also benefits timing behavior and alleviates buffer explosion.
引用
收藏
页码:5599 / +
页数:2
相关论文
共 9 条
[1]  
Alpert C, 1997, DES AUT CON, P588, DOI 10.1145/266021.266291
[2]  
CHOU YC, 2000, P ISPD, P198
[3]  
CONG J, 1999, P INT C COMP AID DES, P358
[4]  
Goplen B, 2005, DES AUT CON, P503
[5]  
JU YC, 1991, 28TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, P541, DOI 10.1145/127601.127729
[6]  
Li C, 2005, ASIA S PACIF DES AUT, P349
[7]   Modeling repeaters explicitly within analytical placement [J].
Saxena, P ;
Halpin, B .
41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, :699-704
[8]   Repeater scaling and its impact on CAD [J].
Saxena, P ;
Menezes, N ;
Cocchini, P ;
Kirkpatrick, DA .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (04) :451-463
[9]  
Sze CN, 2005, DES AUT CON, P509