共 30 条
- [1] Aingaran K., 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), P485, DOI 10.1109/ISQED.2000.838930
- [2] Arunachalam R, 2001, DES AUT CON, P726, DOI 10.1109/DAC.2001.935601
- [3] TACO: Timing analysis with COupling [J]. 37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 266 - 269
- [4] CMOS gate delay models for general RLC loading [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 224 - 229
- [5] Becker E, 1981, FINITE ELEMENTS INTR
- [6] CHEN P, 1999, INT C COMP AID DES, P132
- [7] Analytic models for crosstalk delay and pulse analysis under non-ideal inputs [J]. ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 809 - 818
- [8] Croix JF, 2003, DES AUT CON, P386
- [10] Dartu F, 1997, DES AUT CON, P46, DOI 10.1145/266021.266033