Fractional-N multiplying delay-locked loop with delay-locked loop-based injection clock generation

被引：3
|
作者：
Jee, D. -W. [1 ]
机构：
[1] Ajou Univ, Dept Elect & Comp Engn, Worldcup Ro 206, Suwon 443749, South Korea
来源：
ELECTRONICS LETTERS | 2016年 / 52卷 / 09期
基金：
新加坡国家研究基金会;
关键词：
delay lock loops; clocks; CMOS integrated circuits; fractional-N multiplying delay-locked loop; delay-locked loop-based injection clock generation; multiphase output; output frequency; fractional divider; CMOS; active area; energy efficiency; size; 0; 18; mum; power; 45; muW;
D O I：
10.1049/el.2015.4531
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fractional-N multiplying delay-locked loop (MDLL) with delay-locked loop (DLL)-based injection clock generation is presented. By exploiting multiphase output of DLL which delay is locked to the period of output frequency, the proposed architecture performs a fractional clock multiplication with MDLL, while eliminating deterministic jitter from fractional divider. The proposed MDLL is designed in a 0.18 mu m CMOS process and achieves 31.25 kHz frequency resolution with 1 MHz reference frequency. It occupies an active area of 0.055 mm(2), and consumes 45 mu W for 10 MHz frequency generation, showing energy efficiency figure-of-merit (FoM) of 4.5 mu W/MHz.
引用
收藏
页码：694 / U86
页数：2
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