Implementation of Viterbi Algorithm Based-On Field Programmable Gate Array for Wireless Sensor Network

In general, a data communication transmission consists of data transmitter and data receiver modules. The data transmitter and receiver in the process could show noise between both modulator and demodulator. The data signal noise can emerge error on the data, so it need noise anticipation to correct code in signal. To implement the correction data in this paper implement Viterbi algorithm code on field programmable gate arrays (FPGAs) of Spartan-3E that is configured using very high speed integrated circuit (VHSIC) hardware description language (VHDL) on ISE Xilinx 9.2i application. In this paper shows that the modules consist of four modules, i.e., encoder, noise generator, decoder, and sequence generator modules. In addition, there are three main components of Viterbi decoding algorithm i.e., branch metric computation (BMC), add-compare and select (ACS) and trace-back decoding (TBD). The Viterbi decoder is used in wireless sensor network (WSN) to receiving data that is transmitted by other nodes.