Exploiting FPGA-based architectures and design tools for problems of reconfigurable computations

被引:2
|
作者
Skliarova, I [1 ]
Ferrari, AB [1 ]
机构
[1] Univ Aveiro, Dept Elect & Telecommun, P-3810 Aveiro, Portugal
来源
13TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2000年
关键词
D O I
10.1109/SBCCI.2000.876053
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper addresses the design and implementation,a of a configurable "combinatorial processor", a computational device, which call be used for solving different combinatorial problems. These call be characterized by a set of variables having a limited number of values with a corresponding set of operations that might be applied to these variables. Different mathematical models call be used to describe such tasks. We adopted a matrix representation, which is easier to treat in digital devices. The operations on discrete matrices art unique and cannot be efficiently performed on a general-purpose processor Although the number of such operations grows exponentially with the number of variables, to solve a particular combinatorial problem a very small number of such operations is usually required. Hence the importance of providing for dynamic change of operations. The paper presents an approach allowing the run-time modification of combinatorial computations via reloading the RAM-based configurable logic blocks of the FPGAs.
引用
收藏
页码:347 / 350
页数:4
相关论文
empty
未找到相关数据