A Novel Open-Loop Frequency Estimation Method for Single-Phase Grid Synchronization Under Distorted Conditions

被引：28

作者：

Xiao, Furong ^{[1
]}

Dong, Lei ^{[1
]}

Li, Li ^{[2
]}

Liao, Xiaozhong ^{[1
]}

机构：

[1] Beijing Inst Technol, Sch Automat, Beijing 100081, Peoples R China

[2] Univ Technol Sydney, Fac Engn & Informat Technol, Ultimo, NSW 2007, Australia

来源：

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS | 2017年 / 5卷 / 03期

关键词：

Delayed signal cancellation (DSC); frequency estimation; grid synchronization; phase-locked loop (PLL); transient process smoothing (TPS); POWER CONVERTERS; LOCKED LOOP; FILTER; PLL; ALGORITHM; DESIGN;

D O I：

10.1109/JESTPE.2017.2685620

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new open-loop architecture with good dynamic performance and strong harmonic rejection capability is proposed for single-phase grid synchronization under distorted conditions. Different from previous single-phase grid synchronization algorithms based on the phase-locked loop technique, the proposed method is to estimate the frequency and phase angle of the grid voltage in an open-loop manner so that fast dynamic response and enhanced system stability can be achieved. First, an open-loop frequency estimation algorithm is introduced under ideal grid condition. Then, it is extended to distorted grid voltages through the combination of the developed frequency estimation unit and a prefiltering stage consisting of a second-order low-pass filter and a cascaded delayed signal cancellation (DSC) module. In addition, a transient process smoothing unit is designed to achieve smooth frequency transients in cases where the grid voltage experiences fast and large changes. The working principle of the new frequency estimation algorithm and the developed single-phase grid synchronization approach is given in detail, together with some simulation and experiment results for verifying their performance.

引用

页码：1287 / 1297

页数：11

共 31 条

[1]

[Anonymous], 2012, 2012 IEEE POW EN SOC, DOI DOI 10.1109/PESGM.2012.6345319

[2]

[Anonymous], 2003, IEEE Std 181-2003, DOI [10.1109/IEEESTD.2003.94394, DOI 10.1109/IEEESTD.2003.94285]

[3]

[Anonymous], 2012, 021 CEI

[4]

Ciobotaru M., 2006, P 37 IEEE POW EL SPE, P1511

[5]

Craciun BI, 2012, P INT CONF OPTIM EL, P959, DOI 10.1109/OPTIM.2012.6231767

[6] Estimation of Single-Phase Grid Voltage Parameters With Zero Steady-State Error [J].

Dai, Zhiyong ;

Lin, Wei ;

Lin, Hui .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2016, 31 (05) :3867-3879

[7] Problems of Startup and Phase Jumps in PLL Systems [J].

Ghartemani, Masoud Karimi ;

Khajehoddin, Sayed Ali ;

Jain, Praveen K. ;

Bakhshai, Alireza .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2012, 27 (04) :1830-1838

[8] dq-Frame Cascaded Delayed Signal Cancellation-Based PLL: Analysis, Design, and Comparison With Moving Average Filter-Based PLL [J].

Golestan, Saeed ;

Ramezani, Malek ;

Guerrero, Josep M. ;

Monfared, Mohammad .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2015, 30 (03) :1618-1632

[9] Moving Average Filter Based Phase-Locked Loops: Performance Analysis and Design Guidelines [J].

Golestan, Saeed ;

Ramezani, Malek ;

Guerrero, Josep M. ;

Freijedo, Francisco D. ;

Monfared, Mohammad .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (06) :2750-2763

[10] Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops [J].

Golestan, Saeed ;

Monfared, Mohammad ;

Freijedo, Francisco D. .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2013, 28 (02) :765-778

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