Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Processing

A fully integrated wake-up receiver in 65-nm low-power (LP) CMOS technology is presented. The receiver's RF front end consists of a 40-stage MOS self-mixer using gate biasing to optimize the sensitivity; the baseband circuits use time-encoded analog signals to efficiently implement a matched filter with a DC offset cancellation loop at minimal power consumption. When operating at 434 MHz, the receiver has a -79.1-dBm sensitivity with a 110-ms latency while consuming 420 pW from 0.4 V. When operating at 1.016 GHz with the same latency, the sensitivity is -74 dBm and power consumption is 470 pW.