Gate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiOx interlayer for reliability in sub-micrometer CMOS

The proposed gate electrode structure consists of two stacked large-grain poly-Si layers with an ultra-thin SiO2 interlayer. A CMOS with this gate has two advantages: I) three times larger Q(BD) and a more than ten-fold improvement for V-TH shift in the BT test at 250 degrees C, indicating high tolerance against slow trap generation compared with an as-deposited poly-Si gate, and II) less than 10% gate depletion for both nMOS and pMOS without boron penetration in pMOS. The fabrication of this structure is very compatible with the dual-gate CMOS process.