FAST-CBL: A fast floorplanning algorithm based on corner block list representation

被引：0

作者：

Zeng, YJ ^{[1
]}

Dong, SQ ^{[1
]}

Hong, XL ^{[1
]}

Zeng, YJ ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China

来源：

2004 INTERNATIONAL CONFERENCE ON COMMUNICATION, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEMS | 2004年

关键词：

physical design; floorplanning; corner block list;

D O I：

10.1109/ICCCAS.2004.1346393

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present FAST-CBL, which is a fast floorplanning algorithm based on corner block list representation. By reusing the common largest sub-floorplan of the floorplans of two neighboring solutions in the annealing process, FAST-CBL reduces the overall computations, and thus achieves a significant improvement over the original algorithm. Both theoretical analysis and experimental results demonstrate that our floorplanning algorithm is quite efficient.

引用

页码：1213 / 1217

页数：5

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