A high speed low power CMOS clock driver using charge recycling technique

被引：0

作者：

Bouras, I ^{[1
]}

Liaperdos, Y ^{[1
]}

Arapoyanni, A ^{[1
]}

机构：

[1] NCSR Demokris, Inst Microelect, Aghia Paraskevi 15310, Greece

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an Improved Power-Delay Product (PDP) CMOS clock driver based on the charge recycling technique. Two NMOS pass transistors driven by appropriate control signals are used to accomplish the charge recycling procedure. Simulations have shown an up to 18% improvement of PDP over an equivalent conventional CMOS driver.

引用

页码：657 / 660

页数：4

共 4 条

[1] A 2.2-W, 80-MHZ SUPERSCALAR RISC MICROPROCESSOR
GEROSA, G
GARY, S
DIETZ, C
PHAM, D
HOOVER, K
ALVAREZ, J
SANCHEZ, H
IPPOLITO, P
NGO, T
LITCH, S
ENO, J
GOLAB, J
VANDERSCHAAF, N
KAHLE, J
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) : 1440 - 1454
[2] HAHM M, 1994, P IEEE S LOW POW EL, P60
[3] KyriakisBitzaros ED, 1997, ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV, P1924, DOI 10.1109/ISCAS.1997.621527
[4] A low power charge-recycling CMOS clock buffer
Wang, XH
Porod, W
[J]. NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 238 - 239

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