Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction

This brief provides an efficient method to address both logic errors and crosstalk-induced delay variations. In particular, the inherent skew resulting from parity generation is exploited to ensure that no two adjacent wires switch in opposite directions simultaneously, thereby reducing worst-case on-chip capacitive coupling. Data and parity-check bits are mapped to link driver registers, which are triggered by alternating clock phases. The proposed method reduces worst-case link delay by 25% for a 5 mm link, as compared to a conventional skewed transition approach. Compared with other solutions that simultaneously handle logic and delay errors, the proposed method reduces delay uncertainty by up to 24%, improves residual word error probability by 2.5x, requires fewer wires, and achieves up to 45% and 32% reductions in area and energy consumption, respectively.