Testability analysis and ATPG on behavioral RT-level VHDL

被引：38

作者：

Corno, F ^{[1
]}

Prinetto, P ^{[1
]}

Reorda, MS ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, I-10129 Turin, Italy

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

D O I：

10.1109/TEST.1997.639688

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at rite RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate level ATPGs are often inefficient.

引用

页码：753 / 759

页数：7