Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

被引:13
作者
Kumar, Madam Aravind [1 ]
Chari, Kamsali Manjunatha [2 ]
机构
[1] Grandhi Varalakshmi Venkata Rao Inst Technol Engn, Elect & Commun Engn, Bhimavaram 534207, Andhra Pradesh, India
[2] Gandhi Inst Technol & Management Univ, Elect & Commun Engn, Hyderabad 530045, Telangana, India
关键词
Noise; Wiener filter; real-valued FFT; power spectrum; floating point; VLSI IMPLEMENTATION; FFT; ARCHITECTURE; ERROR; LTE;
D O I
10.1515/jisys-2017-0509
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Speech signals are usually affected by noises during the communication process. For suppressing the noise signal that is combined with the speech signal, a Wiener filter is adapted in digital hearing aids. Weiner filter plays an important role in noise suppression and enhancement by estimating the relation between the power spectra of the noise-affected speech signal and the noise signal. Power consumption and the hardware requirement are the important problems in adapting Weiner filter for major communication systems. In this work, we implemented an efficient Wiener filter and applied it for noise suppression along with a real-valued fast Fourier transform (FFT)/real-valued inverse FFT processor in digital hearing aids. The pipelined process was adopted for increasing the performance of the system. The proposed Wiener filter was designed to remove the iteration problems in the conventional Wiener filter. The division operation was replaced by an efficient inverse and multiplication operation in the proposed design. A modified architecture for matrix inversion with low computation complexity was implemented. The complete design computation was based on IEEE-754 standard single-precision floating-point numbers. TheWiener filter and the whole system architecture was implemented and designed on a Field Programmable Gate Array platform and simulated to validate the results in Xilinx ISE tools. An efficient reduction in power and area was obtained by adapting the proposed method for speech signal noise degradation. The performance of the proposed design was found to be 50.01% more efficient than that of existing designs.
引用
收藏
页码:1360 / 1378
页数:19
相关论文
共 25 条
[1]   Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications [J].
Arunachalam, V. ;
Raj, Alex Noel Joseph .
IET CIRCUITS DEVICES & SYSTEMS, 2014, 8 (06) :526-531
[2]   An In-Place FFT Architecture for Real-Valued Signals [J].
Ayinala, Manohar ;
Lao, Yingjie ;
Parhi, Keshab K. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2013, 60 (10) :652-656
[3]   Hindi phoneme classification using Wiener filtered wavelet packet decomposed periodic and aperiodic acoustic feature [J].
Biswas, Astik ;
Sahu, P. K. ;
Bhowmick, Anirban ;
Chandra, Mahesh .
COMPUTERS & ELECTRICAL ENGINEERING, 2015, 42 :12-22
[4]   Low Complexity Wiener Filtering in CDMA Systems Using a Class of Pseudo-Noise Spreading Codes [J].
Carvajal, Rodrigo ;
Mahata, Kaushik ;
Aguero, Juan C. .
IEEE COMMUNICATIONS LETTERS, 2012, 16 (09) :1357-1360
[5]   New insights into the noise reduction Wiener filter [J].
Chen, Jingdong ;
Benesty, Jacob ;
Huang, Yiteng ;
Doclo, Simon .
IEEE TRANSACTIONS ON AUDIO SPEECH AND LANGUAGE PROCESSING, 2006, 14 (04) :1218-1234
[6]   VLSI Implementation of Auto-Correlation Architecture for Synchronization of MIMO-OFDM WLAN Systems [J].
Cho, Jongmin ;
Kim, Jinsang ;
Cho, Won-Kyung .
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2010, 10 (03) :185-192
[7]   PAPR Reduction of OFDM Using PTS and Error-Correcting Code Subblocking [J].
Ghassemi, Abolfazl ;
Gulliver, T. Aaron .
IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, 2010, 9 (03) :980-989
[8]  
Hong-Yuan Jheng, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, P114, DOI 10.1109/VLSISoC.2011.6081652
[9]   GUSTO: An Automatic Generation and Optimization Tool for Matrix Inversion Architectures [J].
Irturk, Ali ;
Benson, Bridget ;
Mirzaei, Shahnam ;
Kastner, Ryan .
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2010, 9 (04)
[10]   Tiled QR Decomposition and Its Optimization on CPU and GPU Computing System [J].
Kim, Dongjin ;
Park, Kyu-Ho .
2013 42ND ANNUAL INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING (ICPP), 2013, :744-753