An FPGA Design for the Two-Band Fast Discrete Hartley Transform

被引：0

作者：

Pyrgas, Labros ^{[1
]}

Kitsos, Paris ^{[1
]}

Skodras, Athanassios N. ^{[2
]}

机构：

[1] Technol Educ Inst Western Greece, Digital IC dEsign & Syst Lab DICES Lab, Comp & Informat Engn Dept, Antirrion, Greece

[2] Univ Patras, Elect & Comp Engn Dept, Patras, Greece

来源：

2016 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY (ISSPIT) | 2016年

关键词：

Two-Band Fast Discrete Hartley Transform; Field Programmable Gate Array architecture (FPGA); Digital Signal Processing; VHDL;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and reaches a rate of up to 103.82 million samples per second at a 92 MHz clock frequency. The architecture has been implemented using VHDL and realized on a Cyclone IV FPGA of Altera.

引用

页码：295 / 299

页数：5