Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs

被引：4

作者：

Griffoni, Alessio ^{[1
,2
]}

Thijs, Steven ^{[1
,3
]}

Russ, Christian ^{[4
]}

Tremouilles, David ^{[5
,6
]}

Linten, Dimitri ^{[1
]}

Scholz, Mirko ^{[1
,7
]}

Simoen, Eddy ^{[1
]}

Claeys, Cor ^{[1
,3
]}

Meneghesso, Gaudenzio ^{[2
]}

Groeseneken, Guido ^{[1
,3
]}

机构：

[1] Interuniv Microelect Ctr, B-3001 Leuven, Belgium

[2] Univ Padua, Dept Informat Engn, I-35131 Padua, Italy

[3] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium

[4] Infineon Technol AG, D-81721 Munich, Germany

[5] CNRS, LAAS, F-31077 Toulouse, France

[6] Univ Toulouse 2, LAAS, UPS INSA INP ISAE, F-31077 Toulouse, France

[7] Vrije Univ Brussels, Dept Fundamental Elect & Instrumentat, Fac Engn, B-1050 Brussels, Belgium

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2010年 / 10卷 / 01期

关键词：

CMOS; electrostatic discharge (ESD); reliability; silicon-on-insulator (SOI); strain; transmission-line pulse (TLP); ultrathin body (UTB); OXIDE BREAKDOWN; CMOS; RELIABILITY; DEVICES; PERFORMANCE; NMOSFET; STRAIN; IMPACT;

D O I：

10.1109/TDMR.2009.2036156

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical dc parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.

引用

页码：130 / 141

页数：12

共 33 条

[21] Channel width dependence of NMOSFET hot carrier degradation [J].

Li, EH ;

Prasad, S .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (06) :1545-1548

[22]

LU J, 2009, IEDM IN PRESS

[23] Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors [J].

Oh, KH ;

Duvvury, C ;

Banerjee, K ;

Dutton, RW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) :2171-2182

[24] Soft breakdown and hard breakdown in ultra-thin oxides [J].

Pompl, T ;

Engel, C ;

Wurzer, H ;

Kerber, M .

MICROELECTRONICS RELIABILITY, 2001, 41 (04) :543-551

[25]

RAMASWAMY S, 1995, P EOS ESD S, P212

[26] ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies [J].

Russ, Christian .

MICROELECTRONICS RELIABILITY, 2008, 48 (8-9) :1403-1411

[27]

Salman A., 2002, IEEE Transactions on Device and Materials Reliability, V2, P2, DOI 10.1109/TDMR.2002.1014666

[28] ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology [J].

Salman, AA ;

Gauthier, R ;

Putnam, C ;

Riess, P ;

Muhammad, M ;

Ioannou, DE .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2003, 3 (03) :79-84

[29] Carrier-transport-enhanced channel CMOS for improved power consumption and performance [J].

Takagi, Shinichi ;

Irisawa, Toshifurni ;

Tezuka, Tsutomu ;

Numata, Toshinori ;

Nakaharai, Shu ;

Hirashita, Norio ;

Moriyama, Yoshihiko ;

Usuda, Koji ;

Toyoda, Eiji ;

Dissanayake, Sanjeewa ;

Shichijo, Masato ;

Nakane, Ryosho ;

Sugahara, Satoshi ;

Takenaka, Mitsuru ;

Sugiyama, Naoharu .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :21-39

[30]

THIJS S, 2009, P EOS ESD S, P69

← 1 2 3 4 →