A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

被引：73

作者：

Agrawal, Ankur ^{[1
]}

Lee, Sae Kyu ^{[1
]}

Silberman, Joel ^{[1
]}

Ziegler, Matthew ^{[1
]}

Kang, Mingu ^{[1
,8
]}

Venkataramani, Swagath ^{[1
]}

Cao, Nianzheng ^{[1
]}

Fleischer, Bruce ^{[1
]}

Guillorn, Michael ^{[1
]}

Cohen, Matthew ^{[1
]}

Mueller, Silvia ^{[2
]}

Oh, Jinwook ^{[1
,9
]}

Lutz, Martin ^{[1
]}

Jung, Jinwook ^{[1
]}

Koswatta, Siyu ^{[1
]}

Zhou, Ching ^{[1
]}

Zalani, Vidhi ^{[1
]}

Bonanno, James ^{[3
]}

Casatuta, Robert ^{[4
]}

Chen, Chia-Yu ^{[1
]}

Choi, Jungwook ^{[5
]}

Haynie, Howard ^{[6
]}

Herbert, Alyssa ^{[1
]}

Jain, Radhika ^{[1
]}

Kar, Monodeep ^{[1
]}

Kim, Kyu-Hyoun ^{[1
]}

Li, Yulong ^{[1
]}

Ren, Zhibin ^{[1
]}

Rider, Scot ^{[6
]}

Schaal, Marcel ^{[1
]}

Schelm, Kerstin ^{[2
]}

Scheuermann, Michael ^{[1
]}

Sun, Xiao ^{[1
]}

Tran, Hung ^{[1
]}

Wang, Naigang ^{[1
]}

Wang, Wei ^{[1
]}

Zhang, Xin ^{[1
]}

Shah, Vinay ^{[7
]}

Curran, Brian ^{[6
]}

Srinivasan, Vijayalakshmi ^{[1
]}

Lu, Pong-Fei ^{[1
]}

Shukla, Sunil ^{[1
]}

Chang, Leland ^{[1
]}

Gopalakrishnan, Kailash ^{[1
]}

机构：

[1] IBM Res, Yorktown Hts, NY 10598 USA

[2] IBM Corp, Boblingen, Germany

[3] IBM Corp, Austin, TX USA

[4] IBM Corp, Hopewell Jct, NY USA

[5] Hanyang Univ, Seoul, South Korea

[6] IBM Corp, Poughkeepsie, NY USA

[7] IBM Corp, Hursley, England

[8] Univ Calif San Diego, La Jolla, CA 92093 USA

[9] Rebellions, Seoul, South Korea

来源：

2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) | 2021年 / 64卷

关键词：

D O I：

10.1109/ISSCC42613.2021.9365791

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：144 / +

页数：3

共 9 条

[1] DLFloat: A 16-b Floating Point format designed for Deep Learning Training and Inference [J].

Agrawal, Ankur ;

Mueller, Silvia M. ;

Fleischer, Bruce M. ;

Choi, Jungwook ;

Wang, Naigang ;

Sun, Xiao ;

Gopalakrishnan, Kailash .

2019 IEEE 26TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH), 2019, :92-95

[2]

Choi J., P MACH LEARN SYST, P201

[3]

Jiao Y, 2020, ISSCC DIG TECH PAP I, P136, DOI 10.1109/ISSCC19947.2020.9062984

[4]

Lee J, 2019, ISSCC DIG TECH PAP I, V62, P142, DOI 10.1109/ISSCC.2019.8662302

[5]

Lin CH, 2020, ISSCC DIG TECH PAP I, P134, DOI 10.1109/ISSCC19947.2020.9063111

[6]

N VIDIA, NVIDIA A100 TENSOR C

[7]

Oh J., 2020, IEEE S VLSI CIRC

[8]

Sun Xiao, 2019, Advances in Neural Information Processing Systems, V32

[9]

Zimmer B, 2019, SYMP VLSI CIRCUITS, pC300, DOI [10.23919/VLSIC.2019.8778056, 10.23919/vlsic.2019.8778056]

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