Architectural design of an RISC processor for programmable logic controllers

In this paper, an architecture of the RISC processor for programmable logic controllers is proposed. Execution characteristics of relay ladder logic (RLL) are analyzed with various application programs in order to determine an optimal architecture for programmable logic controllers (PLCs). A conditional execution mechanism is developed to prevent pipeline hazards caused by the inherent execution behavior of RLL. Instruction sets of three different architectural models are defined. Translators, assemblers, and simulators are developed for three models to evaluate performance and to choose an optimal architecture for PLCs. The proposed processor, which has an accumulator architecture with a four-stage pipeline, exhibits desirable performance much higher than that of recent commercial PLCs.