A new class of sequential circuits with combinational test generation complexity

被引:23
作者
Fujiwara, H [1 ]
机构
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara 6300101, Japan
关键词
balanced structure; complexity; design for testability; partial scan; reducibility; sequential circuits; test generation;
D O I
10.1109/12.869321
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We introduce a new class of sequential circuits with combinational test generation complexity which we call internally balanced structures. It is shown that sequential circuits can be classified by their structure as follows: {sequential circuits of acyclic structure} superset of {sequential circuits of internally balanced structure} superset of {sequential circuits of balanced structure} and that internally balanced structures allow test generation with combinational test generation complexity. On the other hand, if finite state machines (FSMs) are classified by their realization possibility, it can be shown that {FSMs which can be realized as a sequential circuit of acyclic structure} = {FSMs which can be realized as a sequential circuit of internally balanced structure} superset of {FSMs which can be realized as a sequential circuit of balanced structure}. Hence, any FSM realizable with acyclic structure can be also realized with internally balanced structure which allows test generation with combinational test generation complexity. In addition, we discuss the definition of test generation possibility with combinational test generation complexity and introduce a new definition which covers the previous narrow definition. Finally, we study applications to design for testability based on the partial scan and to test generation time reduction for sequential circuits in general, using characteristics of the internally balanced structures. The experimental results shows the effectiveness of this approach.
引用
收藏
页码:895 / 905
页数:11
相关论文
共 15 条
[11]  
KLAGARIS D, 1993, P DES AUT C, P249
[12]  
LEISERSON CE, 1991, ALGORITHMICA, V6, P5, DOI 10.1007/BF01759032
[13]   Sequential test generation based on circuit pseudo-transformation [J].
Ohtake, S ;
Inoue, T ;
Fujiwara, H .
SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, :62-67
[14]  
Takasaki T, 1998, PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, P211, DOI [10.1109/ASPDAC.1998.669448, 10.1002/(SICI)1520-684X(199810)29:10<26::AID-SCJ3>3.0.CO
[15]  
2-M]