A 10-bit 40MS/s Pipelined ADC with Pre-charged Switched Operational Amplifier

被引：0
|
作者：
Wei, Qi [1 ]
Yang, Huazhong [1 ]
机构：
[1] Tsinghua Univ, Dept Elect Engn, TNList, Beijing 100084, Peoples R China
来源：
ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2 | 2009年
关键词：
analog-to-digital converter; pipeline; switched operational amplifier;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a 10-bit 40MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82mW. The ADC is designed in a 1.8V 1P6M 0.18-mu m CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19dB and Signal to Noise and Distortion Ratio (SNDR) of 60.25dB when a 19.02MHz sinusoidal signal is feed-in.
引用
收藏
页码：394 / 398
页数：5
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