FINE-GRAINED ACTIVATION FOR POWER REDUCTION IN DRAM

被引：33

作者：

Cooper-Balis, Elliott ^{[1
]}

Jacob, Bruce ^{[1
]}

机构：

[1] Univ Maryland, ECE Dept, College Pk, MD 20742 USA

来源：

IEEE MICRO | 2010年 / 30卷 / 03期

关键词：

D O I：

10.1109/MM.2010.43

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

THIS DRAM ARCHITECTURE OPTIMIZATION, WHICH APPEARS TRANSPARENT TO THE MEMORY CONTROLLER, SIGNIFICANTLY REDUCES POWER CONSUMPTION. WITH TRIVIAL ADDITIONAL LOGIC, USING THE POSTED-CAS COMMAND ENABLES A FINER-GRAINED SELECTION WHEN ACTIVATING A PORTION OF THE DRAM ARRAY. EXPERIMENTS SHOW THAT, IN A HIGH-USE MEMORY SYSTEM, THIS APPROACH CAN REDUCE TOTAL DRAM DEVICE POWER CONSUMPTION BY UP TO 40 PERCENT.

引用

页码：34 / 47

页数：14