A novel scaling theory for fully depleted pi-gate (ΠG) MOSFETs

被引:4
作者
Chiang, Te-Kuang [1 ]
机构
[1] Natl Univ Kaohsiung, Dept Elect Engn, Kaohsiung, Taiwan
关键词
Equivalent number of gates (ENG); Natural length; Pi-gate (Pi G) MOSFETs; Drain-induced barrier lowering (DIBL); Control factor; Normalized gate extension depth (NGED);
D O I
10.1016/j.sse.2014.07.012
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel scaling theory for fully depleted pi-gate (Pi G) MOSFETs is presented. The natural length for Pi G MOSFET is obtained by solving the equation of equivalent number of gates (ENG), where the ENG of the Pi G device monitored by the control factor eta can be a linear combination of ENGs for both the triple-gate (TG) and quadruple-gate (QG) transistors. Numerical device simulation data for drain-induced barrier lowering (DIBL) were compared to the model to validate the theory. Among the Pi G devices with the same normalized gate extension depth (NGED = t(ex)/t(si)) in the buried oxide, one with the largest cross-section will show the worst immunity to DIBL effects due to the smallest ENG and largest natural length. For equivalent short-channel gate controlling capability, the Pi G MOSFET with NGED = 0.2 corresponding to the control factor of eta = 0.49 illustrates an improvement of up to 23% in the minimum effective channel length L-min when compared to the double-gate (DG) MOSFET. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:199 / 201
页数:3
相关论文
共 8 条
[1]  
[Anonymous], 2003, DESSIS 3 D 2 D DEV S
[2]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[3]  
Chiang T. K., IEEE T ELECT D UNPUB
[4]   A Novel Scaling Theory for Fully Depleted, Multiple-Gate MOSFET, Including Effective Number of Gates (ENGs) [J].
Chiang, Te-Kuang .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) :631-633
[5]  
Colinge JP, 2008, INTEGR CIRCUIT SYST, P1, DOI 10.1007/978-0-387-71752-4_1
[6]   Device design guidelines for nano-scale MuGFETs [J].
Lee, Chi-Woo ;
Yun, Se-Re-Na ;
Yu, Chong-Gun ;
Park, Jong-Tae ;
Colinge, Jean-Pierre .
SOLID-STATE ELECTRONICS, 2007, 51 (03) :505-510
[7]   Pi-gate SOI MOSFET [J].
Park, JT ;
Colinge, JP ;
Diaz, CH .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (08) :405-406
[8]   SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS [J].
SUZUKI, K ;
TANAKA, T ;
TOSAKA, Y ;
HORIE, H ;
ARIMOTO, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (12) :2326-2329