1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus

被引：7

作者：

Zerbe, JL ^{[1
]}

Chau, PS ^{[1
]}

Werner, CW ^{[1
]}

Thrush, TP ^{[1
]}

Perino, DV ^{[1
]}

Garlepp, BW ^{[1
]}

Donnelly, KS ^{[1
]}

机构：

[1] Rambus Inc, Mt View, CA 94040 USA

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852869

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 1.6Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-mu m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.

引用

页码：128 / 131

页数：4

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