HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter

被引:0
|
作者
Boudabous, Anis
Ben Atitallah, Ahmed [2 ]
Khriji, Lazhar [1 ]
Kadionik, Patrice [2 ]
Masmoudi, Nouri
机构
[1] Sultan Qaboos Univ, Dept Elect & Comp Engn, Muscat, Oman
[2] Univ Bordeaux 1, IMS Lab, F-33405 Talence, France
关键词
Filtering; co-design; FPGA implementation; SoPC; NIOS-II processor;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering problems. This filter is used essentially to remove impulsive and Gaussian noise in colour images. In our design we start by implementing the software solution in system on programmable chip context using NIOS-II softcore processor and mu Clinux as operating system. We evaluate the execution lime of the whole filtering process. Than we add a hardware accelerator part. This latter is implemented using fast parallel architecture. Compared to the software solution results, the use of the hardware accelerator improves clearly the filtering speed and maintains the good filtering quality as shown by simulations.
引用
收藏
页码:70 / 74
页数:5
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