A dynamically reconfigurable IP for data-intensive applications

被引：0
|
作者：
Miyamoto, N [1 ]
Karnan, L [1 ]
Kotani, K [1 ]
Ohmi, T [1 ]
机构：
[1] Tohoku Univ, Grad Sch Engn, Sendai, Miyagi 9808579, Japan
来源：
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS | 2004年
关键词：
D O I：
10.1109/APASIC.2004.1349512
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable JP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.
引用
收藏
页码：404 / 405
页数：2
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