Design of Frequency Modulated Receiver Using Digital Phase Locked Loop

被引：0
|
作者：
Yelne, Pranav N. [1 ]
Karule, Pradeep T. [2 ]
机构：
[1] Rashtrasant Tukadoji Maharaj Nagpur Univ, Yeshwantrao Chavan Coll Engn, Dept Elect Engn, Nagpur, Maharashtra, India
[2] Rashtrasant Tukadoji Maharaj Nagpur Univ, Yeshwantrao Chavan Coll Engn, Nagpur, Maharashtra, India
来源：
2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2015年
关键词：
Booths multiplier; Digital phase locked loop; Numerically Controlled Oscillator; Vertex-6;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, Frequency modulated receiver is designed using Digital phase locked loop circuitry which consists of Booth s multiplier, Loop filter and Numerically controlled oscillator. This design is modeled in Veri log synthesis and performed place and route for design using Xilinx 13.1. In this paper; we design a numerically controlled oscillator that can be tuned to desirable frequency according to the requirement. This design also achieves small area and small power consumption as compared to typical classical method of design.
引用
收藏
页码：889 / 892
页数：4
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