The vector-thread architecture

被引：25

作者：

Krashinsky, R ^{[1
]}

Batten, C ^{[1
]}

Hampton, M ^{[1
]}

Gerding, S ^{[1
]}

Pharris, B ^{[1
]}

Casper, J ^{[1
]}

Asanovic, K ^{[1
]}

机构：

[1] MIT, Comp Sci & Artificial Intelligence Lab, Cambridge, MA 02139 USA

来源：

IEEE MICRO | 2004年 / 24卷 / 06期

基金：

美国国家科学基金会;

关键词：

Cache memory - Computer architecture - Embedded systems - Mathematical models - Performance - Reduced instruction set computing;

D O I：

10.1109/MM.2004.90

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

THE VECTOR-THREAD (VT) ARCHITECTURE SUPPORTS A SEAMLESS INTERMINGLING OF VECTOR AND MULTITHREADED COMPUTATION TO FLEXIBLY AND COMPACTLY ENCODE APPLICATION PARALLELISM AND LOCALITY. VT PROCESSORS EXPLOIT THIS ENCODING TO PROVIDE HIGH PERFORMANCE WITH LOW POWER AND SMALL AREA.

引用

页码：84 / 90

页数：7

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