Chip cooling with integrated carbon nanotube microfin architectures

被引:218
作者
Kordas, K.
Toth, G.
Moilanen, P.
Kumpumaki, M.
Vahakangas, J.
Uusimaki, A.
Vajtai, R.
Ajayan, P. M.
机构
[1] Univ Oulu, Microelect Mat Phys Labs, Dept Elect & Informat Engn, FIN-90014 Oulu, Finland
[2] Univ Oulu, EMPART Res Grp Infotech, FIN-90014 Oulu, Finland
[3] Rensselaer Polytech Inst, Dept Mat Sci & Engn, Troy, NY 12180 USA
[4] Rensselaer Polytech Inst, Rensselaer Nanotechnol Ctr, Troy, NY 12180 USA
基金
芬兰科学院;
关键词
D O I
10.1063/1.2714281
中图分类号
O59 [应用物理学];
学科分类号
摘要
Efficient cooling of silicon chips using microfin structures made of aligned multiwalled carbon nanotube arrays is achieved. The tiny cooling elements mounted on the back side of the chips enable power dissipation from the heated chips on the level of modern electronics demands. The nanotube fins are mechanically superior compared to other materials being ten times lighter, flexible, and stiff at the same time. These properties accompanied with the relative simplicity of the fabrication makes the nanotube structures strong candidates for future on-chip thermal management applications. (c) 2007 American Institute of Physics.
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页数:3
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