IP PROTECTION IN PARTIALLY RECONFIGURABLE FPGAS

被引：16

作者：

Kepa, Krzysztof ^{[1
]}

Morgan, Fearghal ^{[1
]}

Kosciuszkiewicz, Krzysztof ^{[1
]}

机构：

[1] Natl Univ Ireland, Dept Elect Engn, Galway, Ireland

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

D O I：

10.1109/FPL.2009.5272250

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. This paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. This paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.

引用

页码：403 / 409

页数：7