A methodology for product mix planning in semiconductor foundry manufacturing

被引:35
|
作者
Chou, YC [1 ]
Hong, IH [1 ]
机构
[1] Natl Taiwan Univ, Inst Ind Engn, Taipei 106, Taiwan
关键词
bottleneck analysis; product mix planning; semiconductor foundry manufacturing;
D O I
10.1109/66.857936
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Since a semiconductor foundry plant manufactures a wide range of memory and logic products using the make-to-order business model, the product mix is an important production decision. This paper first describes the characteristics of the product mix planning problem in foundry manufacturing that are attributable to the long flow time and queuing network behaviors. The issues of time bucket selection, mix optimization and bottleneck-based planning are next addressed. A decision software system based on integer linear programming techniques and a heuristic procedure has been implemented for mix planning. Data provided by a wafer plant has been used to study problems related to product mix planning. It was determined that the suitable time bucket of planning is either one week or one month and the lead-time offset factor should be included in the logic of workload calculation. This paper also presents various facets of product mix decisions and how they should be integrated with operations management.
引用
收藏
页码:278 / 285
页数:8
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