共 28 条
[1]
[Anonymous], THE GEM5 SIMULATOR
[2]
Burger D, 2000, CSTR1308
[3]
Predicting inter-thread cache contention on a chip multi-processor architecture
[J].
11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS,
2005,
:340-351
[4]
Chang J, 2014, 25 ANN INT C SUP ANN
[5]
Chang JC, 2006, CONF PROC INT SYMP C, P264, DOI 10.1145/1150019.1136509
[6]
Chen XE, 2009, INT S HIGH PERF COMP, P329, DOI 10.1109/HPCA.2009.4798270
[7]
Chiou D, 2000, 430 MIT COMP STRUCT
[8]
Dybdahl H, 2007, INT S HIGH PERF COMP, P2
[9]
Eklov David., 2011, Proceedings of the International Conference on High Performance Embedded Architectures and Compilers, P147, DOI DOI 10.1145/1944862.1944885
[10]
Ghasemzadeh H, 2006, P WORLD AC SCI TECHN, V16