A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical NOR Array Structure

被引：11

作者：

Kim, Yoon ^{[1
]}

Park, Il Han ^{[1
]}

Cho, Seongjae ^{[1
]}

Yun, Jang-Gn ^{[1
]}

Lee, Jung Hoon ^{[1
]}

Kim, Doo-Hyun ^{[1
]}

Lee, Gil Sung ^{[1
]}

Park, Se-Hwan ^{[1
]}

Lee, Dong Hua ^{[1
]}

Sim, Won Bo ^{[1
]}

Kim, Wandong ^{[1
]}

Shin, Hyungcheol ^{[1
]}

Lee, Jong-Duk ^{[1
]}

Park, Byung-Gook ^{[1
]}

机构：

[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2010年 / 9卷 / 01期

关键词：

3-D array; flash memory; silicon-oxide-nitride-oxide-silicon (SONOS); vertical channel;

D O I：

10.1109/TNANO.2009.2026173

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to overcome the limitation of a multibit silicon-oxide-nitride-oxide-silicon (SONOS) memory with multistorage nodes, we propose a unique 3-D vertical NOR (U3VNOR) array architecture. The U3VNOR has a vertical channel so that it is possible to have a long enough channel without extra cell area. Therefore, we can avoid the problems such as redistribution of injected charges, second-bit effect, and short-channel effect. Also, it is the most integrated flash architecture having the smallest unit cell size, which is 1 F-2/bit. In this paper, we present the fabrication method and the operation voltage scheme of the U3VNOR. In addition, through numerical simulation, we verify its program and erase characteristics. Due to its high density and reliable multibit operation, the U3VNOR is a promising structure for the future high-density NOR flash memory.

引用

页码：70 / 77

页数：8

共 18 条

[1]

[Anonymous], 2005, INT TECHN ROADM SEM

[2]

ChenY H, 2006, Technological Development of Enterprise, V25, P54

[3] Highly scalable vertical double gate NOR flash memory [J].

Cho, Hoon ;

Kapur, Pwan ;

Kalavade, Pranav ;

Saraswat, Krishna C. .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :917-+

[4] Establishing read operation bias schemes for 3-D pillar structure flash memory devices to overcome paired cell interference (PCI) [J].

Cho, Seongjae ;

Park, Il Han ;

Lee, Jung Hoon ;

Yun, Jang-Gn ;

Kim, Doo-Hyun ;

Lee, Jong Duk ;

Shin, Hyungcheol ;

Park, Byung-Gook .

IEICE TRANSACTIONS ON ELECTRONICS, 2008, E91C (05) :731-735

[5]

Choi BY, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P118

[6] NROM: A novel localized trapping, 2-bit nonvolatile memory cell [J].

Eitan, B ;

Pavan, P ;

Bloom, I ;

Aloni, E ;

Frommer, A ;

Finzi, D .

IEEE ELECTRON DEVICE LETTERS, 2000, 21 (11) :543-545

[7] Body thickness dependence of impact ionization in a multiple-gate FinFET [J].

Han, Jin-Woo ;

Lee, Jiye ;

Park, Donggun ;

Choi, Yang-Kyu .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (07) :625-627

[8]

HUANG R, 2006, P ICSICT OCT, P709

[9]

KIM K, 2005, P 2005 IEEE INT SOL, P576

[10]

KIM Y, 2008, IEEE SIL NAN WORKSH

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